This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-247700, filed Aug. 17, 2000; and No. 2001-163171, filed May 30, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a redundancy circuit using an anti-fuse and a method for searching for a failed address in a semiconductor memory, and more particularly to a method of this type employed in an integrated circuit such as a semiconductor memory having the redundancy circuit.
2. Description of the Related Art
When manufacturing semiconductor memories, a redundancy system for replacing failed cells with spare cells is indispensable in order to increase the yield of good products. Along conventional manufacture lines, programming is executed to replace failed cells, if found in the last stage of a semiconductor chip manufacturing process, with spare cells using a laser. The resultant semiconductor chips are packaged and subjected to a final test, and good semiconductor memory products are shipped.
However, it is still possible that one- or two-bit failed cells may be found in the final test executed after packaging. The influence of these failed cells upon the product yield cannot be ignored. In light of this, there is a demand for a programming method for replacing failed cells, found after packaging, with spare cells.
Further, in the field of semiconductor memories with various specifications concerning high-speed operation, it has become difficult to manufacture all the memories so that they can operate normally, irrespective of variations in signal transmission timing, due to variations in the precision of the elements. Therefore, timing adjustment is executed after each memory is packaged. In light of this, it is demanded to adjust the signal transmission timings of each packaged semiconductor memory by programming from the outside, and then to fix them permanently.
To meet the demands, there is a method for permanently changing the state of the circuit of each semiconductor memory, using an electric fuse system instead of a laser. The electric fuse system includes a method of using a usual fuse and a method of using an anti-fuse. In the former method, a high voltage is applied to the fuse to thereby break it and hence the wiring pattern of a semiconductor memory. In the latter method, a high voltage is applied to the anti-fuse to create a dielectric breakdown state of an insulating film between wires, i.e. make it conductive.
A description will now be given of a redundancy circuit using the anti-fuse.
FIG. 1 is a circuit diagram illustrating a redundancy circuit using an anti-fuse that consists of a capacitor.
This redundancy circuit creates a programmed state, using a difference between a capacitor in which a high voltage is applied thereto to create its dielectric breakdown state, i.e. make its resistance close to 0, and a capacitor in which no dielectric breakdown occurs whose resistance is almost infinitely great.
As shown in FIG. 1, a power voltage VDD is connected to an end of a capacitor C11 via transistor TR11. The other end of the capacitor C11 is connected to a reference potential (ground potential) GND via transistor TR12. A latch circuit LH11 is connected to a node of the capacitor C11 and the transistor TR11.
In the circuit shown in FIG. 1, if the capacitor C11 as an anti-fuse is dielectrically broken down, its resistance is close to 0, and hence the potential of the node as the input terminal of the latch circuit LH11 is close to the ground level. On the other hand, if the capacitor C11 is not dielectrically broken down, its resistance is almost infinitely great, which means that the node potential of the latch circuit LH11 is close to the power voltage level. Thus, the latching state of the latch circuit LH11 differs depending upon whether or not the capacitor C11 is dielectrically broken down. This example concerns a method of directly determining the input of the latch circuit LH11 on the basis of a difference in voltage level due to a difference in the resistance of the fuse elements.
In this method, however, unless the difference in the resistance of the anti-fuse between its breakdown state and non-breakdown state is not sufficiently large, binary data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d to be latched by the latch circuit LH11 cannot be created reliably. In other words, in the redundancy circuit using the electric fuse system, since the breakdown state of each fuse employed in the fuse system differs depending upon the high voltage applied thereto, the programmed state of each fuse cannot be determined accurately.
The present invention has been developed in light of the above problem and aims to provide a fuse circuit capable of accurately determining the fuse-programmed state irrespective of the breakdown state of a fuse.
The present invention also aims to provide a failed address searching method for efficiently executing the determination of a failed address, necessary for storing the fuse-programmed state in the fuse circuit.
To satisfy the aims, according to a first aspect of the present invention, there is provided a fuse circuit comprising: first and second electric fuses having respective current characteristics changed when a voltage of a predetermined level or more is applied thereto; a differential amplifier for receiving two voltage signals based on the current characteristics of the first and second electric fuses, and outputting a predetermined voltage on the basis of a difference in voltage between the two voltage signals; a memory circuit for storing an output from the differential amplifier; and a switch circuit for connecting and disconnecting the differential amplifier to and from the memory circuit.
To satisfy the aims, according to a second aspect of the present invention, there is provided a fuse circuit comprising: first and second electric anti-fuses having respective leak current characteristics changed when a voltage of a predetermined level or more is applied thereto; a differential amplifier for receiving two voltage signals based on the leak current characteristics of the first and second electric anti-fuses, and outputting a predetermined voltage on the basis of a difference in voltage between the two voltage signals; a memory circuit for storing an output from the differential amplifier; and a switch circuit for connecting and disconnecting the differential amplifier to and from the memory circuit.
To satisfy the aims, according to a third aspect of the present invention, there is provided a fuse circuit comprising: a fuse bit storing circuit having a pair of electric fuses for storing bit information used to determine a circuit operation state, the pair of electric fuses having a first and second electric fuses; a programming control circuit for applying a voltage of a predetermined level or more to one of the electric fuses to thereby make current characteristic states of the electric fuses unbalanced, thereby programming, in the fuse bit storing circuit, the bit information for determining the circuit operation state; a differential amplifier for receiving outputs of the electric fuses and amplifying the unbalanced current characteristic; a memory circuit for storing an output of the differential amplifier; a switch circuit for connecting and disconnecting the differential amplifier to and from the memory circuit; and a detection control circuit for detecting the bit information for determining the circuit operation state programmed in the fuse bit storing circuit.
In the fuse circuit constructed as above, a voltage of a predetermined level or more is applied to one of the electric fuses to thereby make the current characteristic states of the electric fuses unbalanced, and the unbalanced current characteristic states are detected by the differential amplifier. As a result, the programmed states of the first and second electric fuses can be determined accurately irrespective of their breakdown states.
Further, to satisfy the aims, according to a fourth aspect of the present invention, there is provided a failed-address searching method for use in a semiconductor memory that includes a plurality of banks each having a plurality of memory cells provided common address among the plurality of banks, and a plurality of I/O terminals provided for each of the banks for inputting and outputting data to and from the memory cells of the each bank, comprising: reading a plurality of data on the basis of the common address among the banks and the I/O terminals, thereby detecting a failed address of a memory cell storing failed data; and inputting the detected failed address and reading data corresponding to the failed address from each memory cell of the banks, thereby determining that one of the banks which contains the memory cell storing failed data, and that one of the I/O terminals which inputs and outputs data to and from the memory cell storing failed data.
In the above-described failed-address searching method, a plurality of data items are read on the basis of the common address of a plurality of banks and I/O terminals, and subjected to a computing operation, thereby detecting a failed address from the computing operation result and determining the bank including a failed cell and the I/O terminal connected thereto. As a result, a failed address necessary for storing a fuse-programmed state in the fuse circuit can be determined efficiently.